Code: D-09                                                                           Subject: DIGITAL ELECTRONICS

Time: 3 Hours                                                                                                     Max. Marks: 100

NOTE: There are 11 Questions in all.

· Question 1 is compulsory and carries 16 marks. Answer to Q. 1. must be written in the space provided for it in the answer book supplied and nowhere else.

· Answer any THREE Questions each from Part I and Part II. Each of these questions carries 14 marks.

· Any required data not explicitly given, may be suitably assumed and stated.

Q.1       Choose the correct or best alternative in the following:                                           (2x8)

a. When signed numbers are used in binary arithmetic, then which one of the following notations would have unique representation for zero.

(A)  Sign-magnitude.                            (B)  1’s complement.

(C)   2’s complement.                          (D)  9’s complement.

b.

The logic circuit given below (Fig.1) converts a binary code  into

(A) Excess-3 code.                            (B)  Gray code.

(C)  BCD code.                                  (D)  Hamming code.

             c.   The logic circuit shown in the given fig.2 can be minimised to 

(A) (B)

(C) (D)

             d.   In digital ICs, Schottky transistors are preferred over normal transistors because of their

(A) Lower Propagation delay.              (B) Higher Propagation delay.

(C) Lower Power dissipation.              (D) Higher Power dissipation.

             e.   The following switching functions are to be implemented using a Decoder:

                   The minimum configuration of the decoder should be

(A) 2 – to – 4 line.                              (B)  3 – to – 8 line.

(C)  4 – to – 16 line.                            (D)  5 – to – 32 line.

             f.    A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each.  The maximum possible time required for change of state will be

(A) 15 ns.                                          (B)  30 ns.

(C)  45 ns.                                           (D)  60 ns.

             g.   Words having 8-bits are to be stored into computer memory.  The number of lines required for writing into memory are

(A) 1.                                                 (B)  2.

(C)  4.                                                 (D)  8.

             h.   In successive-approximation A/D converter, offset voltage equal to  LSB is added to the D/A converter’s output.  This is done to

(A) Improve the speed of operation.  

(B) Reduce the maximum quantization error.

(C) Increase the number of bits at the output.       

(D) Increase the range of input voltage that can be converted.

PART I

Answer any THREE Questions. Each question carries 14 marks.

Q.2     a.   Convert 2222 in Hexadecimal number.                                                               (4)

             b.   Subtract –27 from 68 using 2’s complements.                                                     (6)

c.   Divide  by .                                                                            (4)

Q.3     a.   State and prove De-Morgan’s theorems.                                                            (5)

b.   Prove the following identities using Boolean algebra:

                   (i)   .

                   (ii)  .

                   (iii)  .                                                                                     (9)

Q.4     a.   A combinational circuit has 3 inputs A, B, C and output F.  F is true for following input combinations

A is False, B is True

                   A is False, C is True

                   A, B, C are False

                   A, B, C are True

      (i)    Write the Truth table for F.  Use the convention True=1 and False = 0.

                   (ii)   Write the simplified expression for F in SOP form.

                   (iii)  Write the simplified expression for F in POS form.

                   (iv)  Draw logic circuit using minimum number of 2-input NAND gates.               (7)

b.   Minimise the logic function

                   Use Karnaugh map.  Draw the logic circuit for the simplified function using NOR gates only.                                                                      (7)

Q.5     a.   What is meant by Wired-AND connection of digital ICs?  What are its advantages and disadvantages.  Draw a circuit of TTL gates with Wired-AND connection and explain its operation. (10)

             b.   What is the necessity of Interfacing in digital ICs and what are the points to be kept in view, while interfacing between TTL gate and CMOS gate?   (4)

  Q.6     a.   Draw the logic diagram of 4-bit odd parity checker using EX-NOR gates and explain its operation with the help of Truth table.                               (7)

b.   Draw the block diagram of 9 to 4 Decimal-to-BCD Priority encoder and explain its operation with the help of Truth table.                                      (7)                                                             

PART II

Answer any THREE Questions. Each question carries 14 marks.

Q.7     a.   What is a Multiplexer Tree?  Why is it needed?  Draw the block diagram of a 32:1 Multiplexer Tree and explain, how is input directed to the output in this system.                                                   (10)

b.   What is a Decoder?  Compare a decoder and a demultiplexer with suitable block diagrams.                                                                      (4)

Q.8     a.   Draw the logic diagram of 4-bit Twisted Ring counter and explain its operation with the help of timing diagram.                                              (6)

             b.   Design a MOD-3 synchronous counter using J-K Flip-Flops.                             (8)

Q.9     a.   Differentiate between static MOS and Dynamic MOS RAM.  Draw the circuit of a static MOS RAM cell and explain its working.                        (10)

             b.   The capacity of 2K  16 PROM is to be expanded to 16 K  16 .  Find the number of PROM chips required and the number of address lines in the expanded memory.                                                             (4)

Q.10           a.                                                        Explain with the help of block diagram, the working of a Dual Slope A/D converter.                                                                                                 (10)

b.  A 6-bit Dual Slope A/D converter uses a reference of –6V and a 1 MHz 

     clock.  It uses a fixed count of 40 (101000).  Find

(i) Maximum Conversion Time.

(ii) Minimum Conversion Rate.                                                        (4)

Q.11           a.                                                        With the help of a neat diagram, explain the working of a weighted-resistor D/A converter.                                                                                       (9)

            b.   A 2-digit BCD D/A converter is a weighted resistor type with           Volt, with , .  Find 

(i) Resolution in Percent and Volts.

(ii) Output for decimal input 82.                                              (5)