Code: C-23 Subject: MICROPROCESSOR BASED SYSTEM DESIGN
Time: 3 Hours Max. Marks: 100
NOTE: There are 11 Questions in all.
· Question 1 is compulsory and carries 16 marks. Answer to Q. 1. must be written in the space provided for it in the answer book supplied and nowhere else.
· Answer any THREE Questions each from Part I and Part II. Each of these questions carries 14 marks.
· Any required data not explicitly given, may be suitably assumed and stated.
Q.1 Choose the correct or best alternative in the following: (2x8)
a. Which of the CPU group listed below have 16-bit internal data registers
(A) 8086, 8088, 80286. (B) 8086, 80286, 80386.
(C) 8088, 80286, 80386. (D) 80286, 80386, 80486.
b. If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is
(A) 2.5 MHz. (B) 5 MHz.
(C) 7.5 MHz. (D) 10 MHz.
c. When the 8086 CPU is reset, it begins executing the software at the following memory location
(A) FFFFF. (B) 00000.
(C) FFFF0. (D) 80000.
d. In which T-state does the CPU sends the address to memory or I/O and the ALE signal for demultiplexing
(A) T1. (B) T2.
(C) T3. (D) T4.
e. If a 
DRAM requires 4
ms for a refresh and has 256 rows to be refreshed, no more than __________ of
time must pass before another row is refreshed.
(A) 64 ms. (B) 4 ns.
(C) 0.5 ns. (D)
15.625 
.
f. Suppose that DS = 1100 h, BX = 0200 h, LIST = 0250 h, the address accessed by the instruction : MOV CL, LIST [BX + SI], (assuming real mode operation) is
(A) 11950 H. (B) 11750 H.
(C) 11700 H. (D) 11900 H.
g. In a DMA write operation the data is transferred
(A) from I/O to memory. (B) from memory to I/O.
(C) from memory to memory. (D) from I/O to I/O.
h. Which type of JMP instruction assembles if the distance is 0020 h bytes
(A) near. (B) far.
(C) short. (D) none of the above.
PART I
Answer any THREE Questions. Each question carries 14 marks.
Q.2 a. Write down two differences between 8086 and 8088 CPU’s. (4)
b. Write a program (using 8086 assembly language) to add two three byte numbers. The first number is stored from 60000 h to 60002 h and the second number is stored from 60003 h to 60005 h. Store the double word result at address 60020 h to 60023 h. Use direct addressing. (5)
c. Repeat the above problem (2b) by using indirect addressing. (5)
In both b & c above, give the flowchart depicting the principle of addition.
Q.3 a. Describe the operation performed by the instruction OUT 47 h, AL. (3)
b. What operation is performed by the following instruction sequence?
MOV DX, B 000 h
MOV DI, 1004 h
MOV CX, 0F h
CLD
REP INS B (3)
c. How is 8055 (Programmable Peripheral Interface) configured if its control register contains 9B h. (3)
d. Write a control word for
counter 1 of 8253 / 8254 that selects the following options: load least
significant byte only, mode 5 of operation and binary counting. Then write an
instruction sequence that will load the control word into 8253 / 8254 that is
located at address 01000 h of memory address space. Assume that 8253 / 8254 is
attached to the I/O bus of the CPU and the address inputs 
and 
are supplied by 
and 
respectively. (5)
Q.4 a. What
are the contents of the data bus and the status of and 
when the following
instructions are executed in 8086
(i) CPU writes a byte 11 h at memory location 1000 : 0002 h.
(ii) CPU writes a word 2211 h at memory location 1000 : 0003 h. (4)
b. Write the functions of the following pins of 8086
(i)
. (ii)
.
(iii) ALE. (iv) Ready. (4)
c. Draw a block diagram to interface two 
SRAM (62128) to the 16-bit
data bus of 8086 based system. Design the address decoder for the address
range from 00000 – 07FFFF h for both the SRAMs. (6)
Q.5 a. What are the limitations of 16-bit ISA bus? (3)
b. What is EISA bus? Write down its salient features. (7)
c. Calculate the time for one PC bus cycle, assuming a 4.77 MHz clock frequency. What is the data transfer rate for the bus? (4)
Q.6 a. List the three types of data that are loaded or stored in memory by the coprocessor. What is the procedure of converting decimal numbers to floating point numbers? (6)
b. Why does 80186 often called embedded controller? (4)
c. ‘Pentium processor has a superscalar architecture’. Explain the meaning of the statement. (4)
PART II
Answer any THREE Questions. Each question carries 14 marks.
Q.7 a. How can one make use of DOS function calls? Explain with the help of an example. (6)
b. Write a short note on :
(i) RTC.
(ii) RS-232-C. (8)
Q.8 a. Explain the terms: simplex, half duplex and full duplex. (6)
b. If the UART(8250) is to generate a serial signal at baud rate of 4800 baud and baud rate divisor is programmed for 240. What is the frequency of the clock? (4)
c. How DRAM’s are different from SRAM’s? Why DRAMs are said to employ address multiplexing? (4)
Q.9 a. Draw and explain the programming model of the processor 80386. (5)
b. Explain the operation of 8279. Explain the following terms:
(i) N key Roll over.
(ii) Key board debounce.
(iii) FIFO RAM. (9)
Q.10 a. Explain how BIU and EU of 8086 allow the fetch and execute cycles to overlap. (4)
b. What are the conditions that will cause EU to enter a ‘Wait State’? (6)
c. What are the differences between CGA and VGA graphics adapters? (4)
Q.11 a. Write down the sequence of events that take place whenever 8086 receives an interrupt. (5)
b. What is difference between Type 0 and Type 1 interrupts of 8086. (4)
c. What do you mean by A/D conversion? Explain any one of the following A/D techniques:
(i) Successive approximation.
(ii) Parallel / flash converter.
(5)