Code: A-09/C-03/T-03 Subject: ANALOG & DIGITAL ELECTRONICS
Time: 3 Hours Max. Marks: 100
NOTE: There are 11 Questions in all.
Question
1 is compulsory and carries 16 marks. Answer to Q. 1. must be written in the
space provided for it in the answer book supplied and nowhere else.
Answer
any THREE Questions each from Part I and Part II. Each of these questions
carries 14 marks.
Any
required data not explicitly given, may be suitably assumed and stated.
Q.1 Choose
the correct or best alternative in the following: (2x8)
a.
The
magnitude response 
of a Butterworth
filter of order N has maximally flat characteristics because
(A) first N derivatives of 
are equal to 0 at 
.
(B)
first N-1derivatives of 
are equal to 0 at 
.
(C) first N-1 derivatives of 
are equal to 0 at 
.
(D) first N derivatives of 
are equal to 0 at 
.
b.
Input
impedance of the OpAmp circuit shown in the fig.1 is
(A)
(B)
.
(C) 
.
(D) 
.
c. Output
for 
dc for the circuit
shown in the
fig.2 will be
(A) 1.0 V.
(B) -0.5 V.
(C) 0.5
V.
(D) 0.0
V.
d. The Boolean expression 
can equivalently be
written, in terms of its minterms, as
(A) 
. (B) 
.
(C) 
. (D) 
.
e. The
T-input of a negative edge triggered has been tied to logic 1. If its clock input is as shown in the fig.3,
then ON and OFF time of its
out will be,
respectively
(A)
0.2
ms and 1.8 ms.
(B)
1.8
ms and 0.2 ms.
(C) 0.5
ms and 0.5 ms.
(D) 1.0
ms and 1.0 ms.
f. Immediately after the inputs to a NAND RS flipflop are simultaneously switched from 00 to 11, the output Q of the flipflop will
(A)
be
equal to 0. (B)
be equal to 1.
(C) race around. (D)
be unpredictable.
g. The
circuit shown in the fig.4 is a
(A) flipflop.
(B) sequential
circuit.
(C) combinational circuit.
(D) parity checker.
h. A MOS differential amplifier has a large gain because
(A) the current through each driver transistor
is a constant.
(B) sum
of currents through both driver transistors is a constant.
(C) the load is a current source and offers
a large resistance.
(D) there
is a no feedback in the circuit.
PART I
Answer
any THREE Questions. Each question carries 14 marks.
Q.2 The OpAmp
shown in the circuit of fig.5 has an open loop gain of 10000, input impedance
of 1MΩ and an output impedance of 1KΩ.
(i) Determine 
if 2.1V is applied
between terminals A and B. (5)
(ii) Find the gain 
of this amplifier. (5)
(iii) Find the gain of the amplifier when the
input has a source resistance of 1KΩ. (4)
Q.3 Consider the function 
.
(i) Draw its pole-zero diagram. (2)
(ii)
Sketch magnitude and phase responses of this function. (4)
(iii) For
K=1, draw a passive circuit to realize H(s). (5)
(iv) Draw
a block diagram circuit to realize this function using integrators, summers and
multipliers. (3)
Q.4 Explain
the working of a 12-bit dual-slope analog to digital converter using
appropriate diagrams and derive the relevant expression for the digital
output. If the input voltage is in
range (0V, 10V) and the counter in the converter is given a clock of 1 MHz,
determine
(i)
the
time taken for output of the integrator to reach its maximum value. (8)
(ii)
conversion
time for input voltage = 5V, assuming reference voltage of 10V. (6)
Q.5 a. Through proper sketches explain the electron density distribution in the base of a n-p-n Bipolar Junction Transistor when
(i) in Active region
(ii) in Saturation.
How
will the explanation be different for a p-n-p transistor? (6)
b. The input voltage V switches from +5V to 10V
in diode circuit shown in the fig.6.
Sketch the current through the diode and explain various regions of this
waveform. (8)
Q.6 With short notes on any TWO of the following:
(i) DC level shifting in OpAmps.
(ii) Sample-and-Hold circuits and their applications.
(iii) Sensitivity of a single OpAmp Biquad.
(iv) MOS operational amplifiers. (14)
PART II
Answer
any THREE Questions. Each question carries 14 marks.
Q.7 a. A portion of TTL gate circuit is shown in the
Fig.7(a), where the transistor Q has 
Base-to-emitter
voltage of the transistor is equal to 0.7V when it is in active region and
0.75V when Q is in saturation.
Determine the output voltage V if the current I=2.5mA. (6)
b. Both NMOS and
PMOS transistors in the circuit of Fig.7(b) have a threshold voltage of 2V and
equal characteristic constants.
Determine the value of input voltage 
and the range of
output voltage for which both transistors will be in saturation. (8)
Q.8 a. Determine the Boolean function implemented by
the multiplexer circuit shown in the fig.8 (a). (4)
b. A
3-to-8 decoder has two enable inputs E1 and
as shown in fig.8
(b). Write a truth table showing the
outputs 
in terms of inputs 
. (5)
c. With the help of
a diagram using Full-adders, explain the working of a 4-bit parallel addition/subtraction of 2s complement
numbers. (5)
Q.9 a. Explain the working of a
positive-edge-triggered Master-Slave JK flipflop. What are its advantages over a normal JK flipflop? If all NAND gates used in the flipflop have
a propagation delay of 5 ns, compute the delay of the Master-Slave. (6)
b. Design
a circuit to generate the sequence 100010 using JK flipflops and logic gates as
required. (8)
Q.10 a.What is the function of the circuit
shown in the fig.9? Explain its
working. (4)
b. Draw the
circuit of a CMOS static RAM cell and explain its operation.
(4)
c. Three negative
edge triggered flipflops having inputs 
, 
and 
respectively, are
connected to make a counter such that 
Starting with 
, what sequence(s) of states will the counter go through? (6)
Q.11 Write short
notes on any THREE of the
following:
(i)
Emitter-Coupled
OR gate.
(ii)
CMOS
logic gates.
(iii)
BJT
inverter.
(iv)
Schottky
diodes and its applications in digital circuits. (14)